The present invention relates to a semiconductor design technology, and more particularly, to a sensing and amplifying circuit included in a phase change memory device and an operation thereof.
Many computer memory technologies have been introduced for storing computer programs and data. Such technologies include a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read only memory (EPROM), and an electrical erasable programmable read only memory (EEPROM). Some of memory technologies require an application of a voltage to retain stored data while others do not require such a voltage application in retaining stored data.
Lately, the demand of a non-volatile memory has increased due to the advantage of the non-volatile memory, which allows repetition of reading/writing data. EEPROM is one type of non-volatile memories. EEPROM uses a floating gate transistor for sustaining electric charges on an insulated floating gate. Each memory cell may be electrically programmed to “1” or “0” by injecting or removing electric charges to or from a floating gate. However, EEPROM has some shortcomings too. For example, it is difficult to reduce memory cells of EEPROM in size, EEPROM is comparatively slow to perform a read operation and a program operation, and EEPROM consumes comparatively large amount of power.
As to another type of non-volatile memory, a phase change memory device is formed of material that electrically changes structured states thereof, each of which represents different electric characteristics. For example, memory devices made of chalcogenide material as germanium·antimony·tellurium mixture (GST). The GST material may be programmed between an amorphous state representing a comparatively high resistivity and a crystalline state representing a comparatively low resistivity (for example, a resistivity lower than the comparatively high resistivity). The GST material is programmed by heating up the GST material. A heating temperature and time are decided depending on whether the GST material is left as an amorphous state or a crystalline state. The high resistivity and low resistivity denote programmed values “1” and “0”. The programmed values can be sensed by measuring the resistivity of the GST material.
In order to perform a write operation for writing data at the GST material, that is, for programming the GST material as an amorphous state or a crystalline state, the structured state of the GST material is changed by applying a comparatively high current to the GST material.
On the contrary, in order to perform a read operation for reading a data value of the programmed GST in the amorphous state or the crystalline state, the resistance value of the GST material is sensed without changing the structured state of the GST material by applying comparatively low current to the GST material.
When a phase change memory device is designed to employ the GST material to form a memory cell, the phase change memory device includes a plurality of phase change memory cells formed of the GST material in an array like a typical semiconductor memory device such as a DRAM including memory cells formed of capacitors in an array.
That is, the phase change memory device performs data input/output operations by selecting one of the plurality of phase change memory cells made of GST material in an array by selection of a word line WL and a bit line BL like a DRAM that performs data input/output operation by selecting one of a plurality of memory cells formed in an array through selection of a word line WL and a bit line BL.
A typical DRAM should be controlled to begin sensing and amplifying data of a selected cell as soon as a word line WL is activated and to sustain this state until the word line WL is inactivated. If the typical DRAM terminates sensing and amplifying data of the selected cell while the word line WL is activated, the data of the selected cell may be impaired. Although the data of selected cell is not broken, refresh characteristics may be deteriorated due to lack of charged electric charge.
As described above, the typical DRAM should continuously retain sensing and amplifying data of a selected cell during the activation period of a word line when data input and output operations are performed by selecting one of a plurality of memory cells in an array.
A phase change memory device may employ the same method of the typical DRAM, which performs sensing and amplifying data of a selected phase change memory cell during the activation period of a word line WL when data is inputted/outputted by selecting one of a plurality of phase change memory cells in the phase change memory cell. When the phase change memory device employs this method, the phase change memory device can normally perform data input/output operations.
However, since a plurality of phase change memory cells are non-volatile, the phase change memory unnecessarily wastes power if the phase change memory continuously performs sensing and amplifying data of a selected phase change memory cell during an activation period of a word line WL when data is inputted/outputted by selecting one of phase change memory cells as in the typical DRAM.
In order words, since the plurality of phase change memory cells in the phase change memory device are non-volatile, a time required for inputting/outputting data is shorter than a time required for activating a word line WL. Therefore, if the phase change memory device continuously performs sensing and amplifying data of a selected phase change memory cell during activation of a word line WL, the phase change memory device unnecessarily wastes power during a time equal to as much as a difference between the time required for activating a word line WL and the time required for inputting/outputting data.